The present invention relates generally to integrated circuit devices, and more particularly a novel technique for detecting electrical shorts on inaccessible nodes of an integrated circuit device using capacitive measurements.
Integrated circuit assemblies are ubiquitous in modern electronic devices, and a large portion of the industrial sector is devoted to the design and manufacture of such devices. As electronic devices are continually being improved and becoming more sophisticated, so are consumers' expectations for the level of quality of these products. Accordingly, new and improved testing techniques are continuously being sought by manufacturers to test the quality of integrated circuits, printed circuit boards, and integrated circuit assemblies after manufacture and prior to shipment of these devices. While testing entails checking many aspects of the product, such as functionality testing and burn-in testing, one of the most important tests after manufacture is basic continuity testing. Continuity testing includes two components: opens testing and shorts testing. Opens testing is performed to ensure that all connections that are supposed to be connected between components of the device (e.g., integrated circuit pins to printed circuit boards, integrated circuit lead wires to pins, traces connections between printed circuit board nodes, etc.) are intact. Shorts testing is performed to ensure that all connections on the device are connected only between nodes that they are intended by design to connect.
Shorts testing uncovers a commonly found defect known as a “shorted connection”, or as used hereinafter, a “short” defect. A short defect is defined as an electrical connection is present between two nodes in the circuit where there should be electrical isolation between the nodes. Short defects typically result from problems in the manufacturing process, such as excess solder due to uneven application of solder paste, the unintentional introduction of conductive particles in the wetting process, etc.
Integrated circuit devices such as integrated circuits, integrated circuit assemblies, printed circuit boards (PCBs), and printed circuit assemblies (PCAs) are typically tested using industrial in-circuit test (ICT) testers. ICT testers are generally equipped with an array of tester interface pins that are configurably connectable to various tester resources (e.g., current sources, voltage sources, measuring devices, etc.). An integrated circuit device may be mounted on a tester fixture that includes a number of probes that connect respective tester interface pins to corresponding respective nodes of the integrated circuit device.
FIG. 1 is a simplified schematic block diagram illustrating a conventional test setup 1 commonly implemented using ICT equipment to test for short defects on an integrated circuit device 13. As illustrated, the integrated circuit device 13 in the example includes four nodes 5, 7, 9, and 11 (labeled N1, N2, N3 and N4). A voltage source 2 is connected via a resistance (R) 3 to node N1. Each of the other nodes N2, N3, and N4 is guarded via connection to ground 12. On a good integrated circuit device 13, no shorts exist and therefore the amount of current flow IS through the resistor 3 is a known value (determined by measurement using a known good board) that depends on the impedance of E1 6. If a short exists between N1 and any of the other nodes N2, N3, or N4, the current IS flowing through the resistor 3 will differ from the expected non-shorted value, most likely by a significant (and therefore detectable) increase. This technique allows detection of a short defect between node N1 and any other grounded node N2, N3, N4. The setup and measurement process is performed for each node 5, 7, 9, 11 (N1, N2, N3, N4) relative to each other node in turn. If none of the current flow measurements differ significantly from the expected non-shorted current value, the integrated circuit device 13 contains no short defects.
The above technique is advantageous in that it is simple and works well as long as all nodes on the integrated circuit device under test are accessible. “Accessible” means the ICT equipment can make an ohmic contact with the node through some kind of probing technique. If this condition cannot be met, the node is “inaccessible”. FIG. 2 illustrates the test setup 15 of FIG. 1 where node N3 of an integrated circuit device 14 is inaccessible. Accordingly, because node N3 is inaccessible and cannot be guarded (by grounding), a short between node N1 and node N3 will not be detected since, because there is no return to ground on node N3, no current will flow through the resistor (R) 3 (i.e., IS=0).
Real world integrated circuit devices such as ICAs, PCBs, and PCAs will typically have a large number of nodes. As stated above, short defects between nodes of an IC device can render the integrated circuit device inoperative or can damage components of the integrated circuit device if the short is between inappropriate nodes.
Many modern integrated circuit devices are losing access due to shrinking geometries. In some cases, the number of nodes on an integrated circuit device exceeds the number of nodes that currently available ICT equipment can contact. These excess non-contacted nodes as well as those that are simply too small to probe are considered inaccessible and cannot be tested using today's methods.
Accordingly, a need exists for a method for diagnosing short defects on inaccessible or non-contacted nodes of an integrated circuit device.